Automotive Innovation ›› 2024, Vol. 7 ›› Issue (1): 82-101.doi: 10.1007/s42154-023-00266-9

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Review of Electrical and Electronic Architectures for Autonomous Vehicles: Topologies, Networking and Simulators

Wenwei Wang1,2, Kaidi Guo1, Wanke Cao1,2, Hailong Zhu3,4, Jinrui Nan1,2 & Lei Yu5    

  1. 1. National Engineering Research Center of Electric Vehicles, Beijing Institute of Technology (BIT), Beijing, 100081, China
    2. Shenzhen Automotive Research Institute, Beijing Institute of Technology (BIT), Shenzhen, 518000, China
    3. State Key Laboratory of Networking and Switching Technology, Beijing University of Posts and Telecommunication, Beijing, 100876, China
    4. Purple Mountain Laboratories, Nanjing, 211111, China
    5. Beijing Kawen New Energy Vehicle Co., LTD, Beijing, 102209, China
  • Online:2024-02-14 Published:2024-02-14

Abstract: With the rapid development of autonomous vehicles, more and more functions and computing requirements have led to the continuous centralization in the topology of electrical and electronic (E/E) architectures. While certain Tier1 suppliers, such as BOSCH, have previously proposed a serial roadmap for E/E architecture development, implemented since 2015 with significant contributions to the automotive industry, lingering misconceptions and queries persist in actual engineering processes. Notably, there are concerns regarding the perspective of zone-oriented E/E architectures, characterized by zonal concentration, as successors to domain-oriented E/E architectures, known for functional concentration. Addressing these misconceptions and queries, this study introduces a novel parallel roadmap for E/E architecture development, concurrently evaluating domain-oriented and zone-oriented schemes. Furthermore, the study explores hybrid E/E architectures, amalgamating features from both paradigms. To align with the evolution of E/E architectures, networking technologies must adapt correspondingly. The networking mechanisms pivotal in E/E architecture design are comprehensively discussed. Additionally, the study delves into modeling and verification tools pertinent to E/E architecture topologies. In conclusion, the paper outlines existing challenges and unresolved queries in this domain.